A CMOS integrated circuit is a type of MOSFET integrated circuit which has both N-channel and P-channel transistors embodied therein. It is frequently desirable to increase the functionality of such an integrated circuit without increasing the number of its external pins or terminals.
In the past, various circuits and schemes have been devised for CMOS integrated circuits and for single-polarity MOSFET integrated circuits to minimize the required number of external terminals. One commonly-used scheme is the sharing of an external terminal as an input and output.
Another approach for minimizing the number of pins is use of a trinary input circuit at an input terminal. The trinary input circuit has two outputs and produces different logic states depending upon whether the input terminal has a logic 1 applied, a logic 0 applied, or is left floating. In CMOS integrated circuits, however, it is frequently undesirable to leave an input floating.
Another scheme, which may be used advantageously in single-polarity MOSFET integrated circuits, utilizes circuitry on the integrated circuit for detecting when a voltage substantially greater than the power supply voltage is applied to an input terminal. The detection of the application of such an unusual voltage condition can be utilized by on-chip logic to cause the integrated circuit to function differently than under usual conditions. This can be especially useful for testing purposes.
Such a high-input-voltage scheme can be implemented by connecting an input terminal not only to the inputs of conventional logic gates on the integrated circuit but also to the gate electrode of an on-chip enhancement-mode MOSFET transistor having an exceptionally high threshold voltage. The threshold voltage of the transistor is made somewhat higher than the power supply voltage in order for the transistor to remain non-conductive when a normal logic 1 or logic 0 is applied to the input, but to become conductive when a voltage substantially greater than that of the power supply is applied. Other on-chip circuitry can readily determine that the high-threshold-voltage transistor has become conductive, thereby detecting that a higher than usual voltage condition is applied to the input terminal. Alternative circuits for detecting the application of a higher than usual voltage at an input include circuits which utilize simple resistive voltage dividers in conjunction with normal-threshold-voltage MOSFET transistors and circuits which utilize series-connected stacks of normal-threshold-voltage MOSFET transistors.
In the usual CMOS integrated circuit case, though, the application of an exceptionally high voltage to an input is impracticable because there usually is an on-chip diode connected between the input and the integrated circuit's power supply node. The diode may be connected by design as part of an electrostatic discharge protection scheme or may exist simply as a consequence of the physical structure of the integrated circuit. A commonly-used CMOS integrated circuit structure, for example, utilizes an N-type substrate in which the sources and drains of all the P-channel transistors are disposed. In such a structure, the source and drain regions of the N-channel transistors are disposed in either common or separate P-wells which, in turn, are disposed in the N-type substrate. These P-wells comprise the P-type substrate regions for the N-channel transistors. In conventional circuitry, the P-wells are connected to a ground potential and the N-type substrate is connected to the most positive power supply node in order that the diodes formed by the P-wells and the N-type substrate is always back-biased. When an input terminal is connected to a P region disposed in the N-type substrate, the forward-bias voltage-clamping action of the diode formed between such a P region and the N-type substrate prevents the input voltage from being taken to a voltage substantially more positive than that which is applied to the N-type substrate.
In accordance with the foregoing, a need exists for a simple input circuit which can be practicably used with CMOS integrated circuits to increase functionality of the integrated circuit without necessitating an increase in the number of external pins or terminals.